Low bit-error-rate (BER) communication of data over a communications channel is often considered an important requirement in many systems. The BER is a function of many parameters, including a phase of a clock signal or phases of clock signals. An incorrect phase or timing of a respective clock signal may reduce a timing margin and/or increase the BER. As a consequence, communications devices and systems often include components, such as phase locked loops, delay locked loops and phase interpolators, that allow the phase of the respective clock signal to be adjusted. For example, a phase interpolator may generate the respective clock signal having the phase that corresponds to a control signal applied to the phase interpolator. The control signal may specify a phase step or setting.
Unfortunately, there may be nonlinearities or errors in a mapping from the phase code or step to the phase of the respective clock signal. Resulting phase errors may adversely impact the device and/or system performance, as discussed above. As a consequence, testing of such nonlinearities (or the converse, timing linearity) is often included in the characterization and acceptance of devices, such as integrated circuits. This testing is often performed using dedicated, external test equipment. Such test equipment, however, is often expensive. The accuracy and/or repeatability of the test equipment may be insufficient. And testing for nonlinearities over a wide range of phase steps may be time consuming, thereby further increasing the expense.
There is a need, therefore, for improved testing equipment for characterizing phase linearity.
Like reference numerals refer to corresponding parts throughout the drawings.